Conventional semiconductor devices generally include a semiconductor substrate, such as a silicon substrate, and a plurality of sequentially formed dielectric interlayers within which conductive paths or interconnects made of conductive materials are fabricated. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using vias or contacts. Copper and copper-alloys have recently received considerable attention as interconnect materials for integrated circuits because of their superior electro-migration and low resistivity characteristics. The interconnects are usually formed by filling copper in features or cavities etched into the dielectric layers by a deposition process. The preferred method of copper deposition is electrochemical deposition. Since copper is an important interconnect material, it will be used as the example to describe this invention. It should be appreciated that the invention may be used for the deposition of many other materials such as Ni, Co, Pt, Pb etc.
In a typical process, first an insulating layer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features or cavities such as trenches and vias in the insulating layer. Then, a barrier/glue layer and optionally a seed layer are deposited over the patterned surface and a conductor such as copper is electroplated to fill all the features. However, the plating process, in addition to filling the features with copper, also deposits excess copper over the top surface of the substrate. This excess copper is called an “overburden” and it is removed during a subsequent process step, which may be a chemical mechanical polishing (CMP) step, an electropolishing step, or electrochemical mechanical polishing step among others.
During the copper electrodeposition process, specially formulated acidic plating solutions or electrolytes are commonly used. These electrolytes typically contain water, acid (such as sulfuric acid), ionic species of copper, chloride ions and certain organic additives, which affect the properties and the plating behavior of the deposited material. Typical electroplating baths contain at least two of the many types of commercially available additives such as accelerators, suppressors and levelers. It should be noted that these additives are sometimes called different names. For example, the accelerator may be referred to as a brightener and the suppressor as a carrier or inhibitor in the literature. Levelers, which are a certain type of inhibitors, may also be employed. Functions of these additives in the electrolyte and the role of the chloride ion are widely known in the field, although the details of the mechanisms involved may not be fully understood or agreed upon.
FIG. 1A shows an exemplary interconnect structure after the copper plating step. The substrate 10 includes small features 12 such as high aspect ratio vias or trenches. The features are formed into a dielectric layer 16. The dielectric layer 16 has a top surface 18. The features and the surface of the dielectric are coated with a barrier/glue or adhesion layer 20 and a copper seed layer 22. The barrier layer 20 may be made of Ta, TaN or combinations of any other materials that are commonly used in copper electrodeposition. The seed layer 22 is deposited over the barrier layer 20, although for specially designed barrier layers there may not be a need for a seed layer. After depositing the seed layer 22, copper is electrodeposited thereon from a suitable plating bath to form the copper layer 24. During this step, an electrical contact is made to the copper seed layer 22 and/or the barrier layer 20 so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown) of the electrodeposition system. The copper is electrodeposited using the specially formulated plating solutions, as discussed above. By adjusting the amounts of the additives, such as the chloride ions, suppressor/inhibitor, leveler, and the accelerator, it is possible to obtain bottom-up copper film growth in the small features 12 without defects such as voids or seams. FIG. 1B shows an unsuccessful gap-fill that has resulted in a void/seam defect 26 in an exemplary via 27. For simplicity, barrier and seed layers are not shown in this figure.
Gap fill into high aspect ratio features is a strong function of additives and plating conditions. Additive adsorption on surfaces, their mass transport to location of the via, their distribution and concentrations are all factors that can influence gap fill. Defects such as the one shown in FIG. 1B cause reliability and yield problems in interconnect structures and cannot be tolerated. Therefore, uniformity of gap fill throughout the wafer surface is critical. Since the linear velocities of different points on the surface of a rotating wafer in a process solution are different, mass transfer, additive distribution may also be different from point to point. This, in turn, causes differences in the gap-fill capability at the center and edge regions of the wafer. Features may be filled well at the center and not well near the edges. Alternately gap-fill may be perfect near the edges and not good near the center.
Resistivity or sheet resistance of interconnects is another important factor. Interconnects introduce RC time constant and delay to the operation of integrated circuits. Therefore, resistance and capacitance of interconnect structures need to be as low as possible. Electrodeposited conductors such as Cu and Cu alloys typically have small grain size in their as-deposited form. For example, Cu layers plated out of commonly used electrolytes containing organic and inorganic additives have grain sizes, which are typically smaller than 0.2 μm. Therefore, the sheet resistance of such layers is high compared to bulk copper values. For example, the resistivity of as-plated copper may be as high as 2.5 μohm-cm. When such films are stored at around room temperature for a period of time, however, the grain size increases due to a self-annealing or re-crystallization phenomenon, and the resistivity decreases, typically by about 20%. Re-crystallization process may be accelerated by applying higher heat to the wafers. Therefore, grain size of electroplated copper layers may be increased and their resistivity may be decreased by annealing the films at a temperature range of 20–500° C., preferably between 90° C. and 400° C. Since sheet resistance of electroplated copper layers decreases as their grain size increases, sheet resistance measurements are typically used to monitor re-crystallization of such films.
Long term reliability of copper interconnect structures is affected, among other factors, by the micro-structure, defectiveness, grain size, crystalline orientation or texture, resistivity and impurity content of the copper material within the interconnect features such as lines and vias. For example, large grain size is important for higher electromigration resistance and better stress migration property of interconnect structures. As described before, low sheet resistance is desirable to reduce the RC time constant. Sheet resistance or grain size differences on a wafer give rise to lower yields. Uniformity of these important parameters throughout the wafer surface is essential for better reliability and high yield.
In a typical wafer plating apparatus, wafer is rotated during plating. On a rotating substrate linear velocity increases in a radial fashion from the center of the wafer where the velocity is zero. Therefore, for a given solution flow rate, the relative velocity between the plating solution and the wafer surface is also variable on the wafer surface. This velocity differential gives rise to a difference in mass transfer at the center of the wafer versus the edge. The difference in mass transfer results in a difference in the quality of the deposited film since mass transfer plays an important role in bringing copper ions and additive species to the surface that is being plated. For example, in copper films deposited in conventional apparatus with conventional method of rotating wafers, re-crystallization rate of the central portion of the film is different than the re-crystallization rate of the edge region. Typically this radial variation is such that re-crystallization is more rapid at the edge of the wafer and decreases towards the center (see for example, M. E. Gross et al., Conference Proceedings ULSI XV, 2000 Materials Research Society, page: 85, and Malhotra et al. Conference Proceedings ULSI XV, 2000 Materials Research Society, page: 77). This is exemplified in FIG. 2, which schematically shows the variation of sheet resistance as a function of time at room temperature at the edge and center of a plated wafer. As can be seen from FIG. 2, the starting sheet resistance of as-plated copper film is high at time zero. Edge regions self-anneal in a time period of t1 and sheet resistance goes down to a stabilized lower value of R, whereas the edge regions take much longer until time t2 to approach this low resistance value. Typical times for re-crystallization may change from a few hours to a few days depending upon the additive concentrations, plating conditions and film thickness. For the example in FIG. 2, t1 may be in the order of 10–30 hours, whereas t2 may be in the order of 90–200 hours. Changes in re-crystallization times have also been correlated with change of stress and texture in Cu films. Therefore, non-uniformities observed in re-crystallization also suggest non-uniformities in texture and stress.
Although there is no conclusive understanding of this non-uniformity over the wafer surface, there have been various explanations. For example, Malhotra et al. reference mentioned above attributed the radial non-uniformity in the re-crystallization of electroplated Cu films to a radial distribution of plating impurities. M. E. Gross et al. stated that the radial variation in re-crystallization decreasing from the edge of the wafer is likely related to processing conditions that affect the surface interactions of additives. It should be appreciated that the varying linear velocity on the wafer surface can influence mass transfer and additive surface interactions and give rise to the observed non-uniformities.
It is therefore necessary, for better yields and reliability, to develop new processing tools and approaches to improve the uniformity of electroplated film properties and the uniformity of gap-fill capability.